Implementing Evolution of FIR-Filters Efficiently in an FPGA
نویسندگان
چکیده
Reconfigurable hardware devices make it possible to change the topology of electronic circuits at runtime. Using reconfigurable devices as a platform for Evolvable hardware (EHW) is well suited for real-time adaptive systems. This paper contains a novel approach on how to evolve the parameters for an adaptive digital filter. Both the filter as well as the evolution is implemented in a single Field programmable gate array (FPGA). The circuit is based on context-switching in FPGA-devices and preliminary results indicate a compact hardware as well
منابع مشابه
Supremacy of Differential Evolution Algorithm in Designing Multiplier-Less Low-Pass FIR Filter
In this communication, we have made an attempt to design multiplier-less low-pass finite impulse response (FIR) filter with the aid of various mutation strategies of Differential Evolution (DE) algorithm. Impulse response coefficient of the designed FIR filter has been represented as sums or differences of powers of two. Performance of the proposed filter has been evaluated in terms of its freq...
متن کاملEfficient Hardware Implementation of Digital Filters using Distributed Arithmetic (DA)
The FPGA (Field Programmable Gate Array) constitute of many programmable modules like Configuration Logic Blocks (CLBs), Block Random Access Memories (BRAM), DSP 48 blocks and Input/output (I/O) modules. The CLBs are the main programmable logic units which consist of different number of logic slices and each slice contains different number of LUTs and flips flops depending upon the FPGA device ...
متن کاملImplementing High-Order FIR Filters in FPGAs
Contemporary field-programmable gate arrays (FPGAs) are predestined for the application of finite impulse response (FIR) filters. Their embedded digital signal processing (DSP) blocks for multiply-accumulate operations enable efficient fixed-point computations, in cases where the filter structure is accurately mapped to the dedicated hardware architecture. This brief presents a generic systolic...
متن کاملD Esign and I Mplementation of 120 O Rder Fir F Ilter Based on Fpga
Distributed algorithm is suitable for FPGA to do multiply-accumulate operations, which use the abundant memory resources of FPGA to do look-up table operation. We present a method for implementing high speed Finite Impulse Response (FIR) filters using just registered adders and hardwired shifts. We extensively use a modified common sub expression elimination algorithm to reduce the number of ad...
متن کاملHardware Description of Digital Adaptive IIR Filters for Implementing on FPGA
The hardware description and implementation of adaptive infinite-impulse-response (IIR) filters for real-time applications is an important and challenging designing issue. The aim of this paper is hardware description of digital adaptive IIR filters for implementing on field programmable gate array (FPGA) chips. The direct architecture is considered for IIR filter designing and Equation-Error (...
متن کامل